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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES +2.5 V to +5.5 V Supply Operation 50MHz Serial Interface 10MHz Multiplying Bandwidth 10V Reference Input 10-Lead SOIC Package Pin Compatible 8, 10 and 12 Bit Current Output DACs Guaranteed Monotonic Four Quadrant Multiplication Power On Reset Daisy Chain Mode Readback Function 5A typical Power Consumption APPLICATIONS Portable Battery Powered Applications Waveform Generators Analog Processing Instrumentation Applications Programmable Amplifiers and Attenuators Digitally-Controlled Calibration Programmable Filters and Oscillators Composite Video Ultrasound Gain, offset and Voltage Trimming
High Bandwidth CMOS 8/10/12-Bit Serial Interface Multiplying DACs AD5426/AD5432/AD5443*
FUNCTIONAL BLOCK DIAGRAM
VDD
VREF
R
8/10/12 BIT R-2R DAC
RFB IOUT1 IOUT2
AD5426/ AD5432/ AD5443
DAC REGISTER
Power On Reset
INPUT LATCH
SYNC SCLK SDIN
CONTROL LOGIC & INPUT SHIFT REGISTER
SDO
GND
GENERAL DESCRIPTION
The AD5426/AD5432/AD5443 are CMOS 8, 10 and 12-bit Current Output digital-to-analog converters respectively. These devices operate from a +2.5 V to 5.5 V power supply, making them suited to battery powered applications and many other applications. These DACs utilize double buffered 3-wire serial interface that is compatible with SPITM, QSPITM, MICROWIRETM and most DSP interface standards. In addition, a serial data out pin (SDO) allows for daisy chaining when multiple packages are used. Data readback allows the user to read the contents of the DAC register via the SDO pin. On power-up, the internal shift register and latches are filled with zeros and the DAC outputs are at zero scale. As a result of manufacture on a CMOS sub micron process, they offer excellent four quadrant multiplication
*US Patent Number 5,689,257 SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
characteristics, with large signal multiplying bandwidths of 10MHz. The applied external reference input voltage (VREF) determines the full scale output current. An integrated feedback resistor (RFB) provides temperature tracking and full scale voltage output when combined with an external Current to Voltage precision amplifier. The AD5426/AD5432/AD5443 DACs are available in small 10-lead SOIC packages.
PRODUCT HIGHLIGHTS
1. 2. 3.
10MHz Multiplying Bandwidth 3mm x 5mm 10-lead SOIC package Low Voltage, Low Power Current Output DACs.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443-SPECIFICATIONS1noted. DC performance measured with (V = 2.5 V to 5.5 V, V = +10 V, I x = O V. All specifications T to T unless otherwise
DD REF OUT MIN MAX
OP1177, AC performance with AD811 unless otherwise noted.)
Parameter
STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5426 AD5432 AD5443 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5
2 2
Min
Typ
Max
Units
Conditions
8 0.5 1 10 1 1 12 2 1 2 5 10 50 TBD 10 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, I OUT1 nA Data = 0000H, IOUT1 V V k V V V A pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 100 mV rms, DAC loaded all 1s VREF = 6 V rms, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. DAC latch alternately loaded with 0s and 1s.
-75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001
ns ns ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 6 V rms, All 1s loaded, f = 1kHz VREF = 5 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA Single Supply Operation (Biased Mode) AD5426/AD5432/AD5443
(VDD = 2.5 V to 5.5 V, VREF = + 2V, IOUT2 = +1 V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD811 unless otherwise noted.)
Parameter
STATIC PERFORMANCE AD5426 Resolution Relative Accuracy Differential Nonlinearity AD5432 Resolution Relative Accuracy Differential Nonlinearity AD5443 Resolution Relative Accuracy Differential Nonlinearity Gain Error Gain Error Temp Coefficient2 Output Leakage Current Output Voltage Compliance Range REFERENCE INPUT Reference Input Range VREF Input Resistance DIGITAL INPUTS/OUTPUT Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIL Input Capacitance VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH DYNAMIC PERFORMANCE2 Reference Multiplying BW Output Voltage Settling Time AD5426 AD5432 AD5443 Slew Rate Digital to Analog Glitch Impulse Multiplying Feedthrough Error Output Capacitance Digital Feedthrough Total Harmonic Distortion Output Noise Spectral Density SFDR performance Intermodulation Distortion POWER REQUIREMENTS Power Supply Range IDD Power Supply Sensitivity 2 2.5
2 2
Min
Typ
Max
Units
Conditions
8 0.5 1 10 1 1 12 2 1 2 5 10 50 TBD tbd 10
Bits LSB LSB Bits LSB LSB
Guaranteed Monotonic
Guaranteed Monotonic
Bits LSB LSB Guaranteed Monotonic mV ppm FSR/C nA Data = 0000H, TA = 25C, IOUT1 nA Data = 0000H, IOUT1 V V k V V V A pF V V V V MHz MHz
8 1.7
12
Input resistance TC = -50ppm/C VDD = 2.5 V to 5.5 V VDD = 2.7 V to 5.5 V VDD = 2.5 V to 2.7 V
0.8 0.7 1 10 0.4 VDD - 1 0.4 VDD - 0.5 10 TBD 30 35 40 100 3 TBD TBD TBD
ISINK = 200 A ISOURCE = 200 A ISINK = 200 A ISOURCE = 200 A VREF = 100 mV rms, DAC loaded all 1s VREF = 1 V, DAC loaded all 1s Measured to 1/2 LSB. RLOAD = 100, CLOAD = 15pF. VREF = 0V,DAC latch alternately loaded with 0s & 1s.
-75 2 4 5 -85 -85 25 72 TBD 5.5 10 0.001
ns ns ns V/s nV-s dB pF pF nV-s dB dB nV/Hz dB dB V A %/%
1 LSB change around Major Carry DAC latch loaded with all 0s. Reference = 10kHz. DAC Latches Loaded with all 0s DAC Latches Loaded with all 1s Feedthrough to DAC output with SYNC high and Alternate Loading of all 0s and all 1s. VREF = 2 Vp-p, 1V Bias, All 1s loaded, f = 1kHz VREF = 2 V, Sinewave generated from digital code. @ 1kHz
Logic Inputs = 0 V or VDD VDD = 5%
NOTES 1 Temperature range is as follows: B Version: -40C to +105C. 2 Guaranteed by design and characterisation, not subject to production test. Specifications subject to change without notice.
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PRELIMINARY TECHNICAL DATA
AD5426/AD5432/AD5443-SPECIFICATIONS1 (V = 2.5 V to 5.5 TIMING CHARACTERISTICS1 otherwise noted.) V, V = +5 V, I 2 = O V. All specifications T
DD REF OUT
MIN
to TMAX unless
Parameter fSCLK t1 t2 t3 t42 t5 t6 t7 t8 t93
Limit at TMIN, TMAX 50 20 8 8 13 5 4.5 5 30 25
Units MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min
Conditions/Comments Max Clock frequency SCLK Cycle time SCLK High Time SCLK Low Time SYNC falling edge to SCLK active edge setup time Data Setup Time Data Hold Time SYNC rising edge to SCLK active edge Minimum SYNC high time SCLK Active edge to SDO valid
NOTES 1 See Figures 1 & 2. Temperature range is as follows: B Version: -40C to +105C. Guaranteed by design and characterisation, not subject to production test. All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. 2 Falling or Rising edge as determined by control bits of Serial word. 3 Daisychain and Readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3. Specifications subject to change without notice.
t1 SCLK t2 t8 t4 SYNC t6 t5 DIN DB16 DB0 t3 t7
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Stand Alone Mode Timing Diagram.
t1 SCLK t2 t4 SYNC t6 t3 t7
t8
t5 SDIN DB16 (N)
DB0 (N) t9
DB16 (N+1)
DB0 (N+1)
SDO
DB16(N)
DB0(N)
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Daisy Chain and Readback Modes Timing Diagram
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
ABSOLUTE MAXIMUM RATINGS1,
(TA = +25C unless otherwise noted)
2
VDD to GND -0.3 V to +7 V VREF, RFB to GND -12 V to +12 V IOUT1, IOUT2 to GND -0.3 V to +7 V 10 mA Input Current to any pin except supplies Logic Inputs & Output3 -0.3V to VDD +0.3 V Operating Temperature Range Industrial (B Version) -40C to +105C Storage Temperature Range -65C to +150C Junction Temperature +150C 206C/W 10 lead SOIC JA Thermal Impedance Lead Temperature, Soldering (10seconds) 300C IR Reflow, Peak Temperature (<20 seconds) +235C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Transient currents of up to 100mA will not cause SCR latchup. 3 Overvoltages at SCLK, SYNC, DIN, will be clamped by internal diodes. Current should be limited to the maximum ratings given.
200uA TO OUTPUT PIN
IOL VOH (MIN) + VOL (MAX)
CL 50pF 200uA IOH
2
Figure 3. Load Circuit for SDO Timing Specifications
ORDERING GUIDE
Model AD5426BRM AD5432BRM AD5443BRM
Temperature Range -40 C to +105 C -40 oC to +105 oC -40 oC to +105 oC
o o
Package Description SOIC SOIC SOIC
Branding D01 D02 D03
Package Option RM-10 RM-10 RM-10
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
PIN FUNCTION DESCRIPTION
Pin 1 2 3 4
Mnemonic I OUT 1 IOUT2 GND SCLK
Function DAC Current Output. DAC Analog Ground. This pin should normally be tied to the analog ground of the system. Ground Pin. Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is clocked into the shift register on the rising edge of SCLK. Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default, on power up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to rising edge. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input shift register is enabled. Data is loaded to the shift register on the active edge of the following clocks. In stand alone mode, the serial interface counts clocks and data is latched to the shift register on the 16th active clock edge. Serial Data Output. This allows a number of parts to be daisychained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked out on the alternate edge to loading data to the shift register. Writing the Readback control word to the shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the opposite edges to the active clock edge. Positive power supply input. These parts can be operated from a supply of +2.5 V to +5.5 V. DAC reference voltage input pin. DAC feedback resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.
5
SDIN
6
SYNC
7
SDO
8 9 10
VDD VREF RFB
PIN CONFIGURATION SOIC
IOUT1 1 IOUT2 2 GND 3 AD5426/ AD5432/ AD5443 (Not to Scale)
10 RFB 9 VREF 8 VDD 7 SDO 6 SYNC
SCLK 4 SDIN 5
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
TERMINOLOGY Relative Accuracy Intermodulation Distortion
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.
Differential Nonlinearity
The DAC is driven by two combinded sine waves references of frequencies fa and fb. Distortion products are produced at sum and difference frequencies of mfanfb where m, n = 0, 1, 2, 3... Intermodulation terms are those for which m or n is not equal to zero. The second order terms include (fa +fb) and (fa - fb) and the third order terms are (2fa + fb), (2fa -fb), (f+2fa + 2fb) and (fa 2fb). IMD is defined as IMD = 20log (rms sum of the sum and diff distortion products)
rms amplitude of the fundamental
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
Gain Error
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the device will provide the specified characteristics.
GENERAL DESCRIPTION DAC SECTION
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current which flows in the DAC ladder switches when these are turned off. For the IOUT1 terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT1 current. Minimum current will flow in the IOUT2 line when the DAC is loaded with all 1s
Output Capacitance
The AD5426, AD5432 and AD5443 are 8, 10 and 12 bit current output DACs consisting of a standard inverting R2R ladder configuration. A simplified diagram for the 8Bit AD54246 is shown in Figure 4. The feedback resistor RFB has a value of R. The value of R is typically 10k (minimum 8k and maximum 12k). If IOUT1 and IOUT2 are kept at the same potential, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at VREF is always constant.
R
VREF
Capacitance from IOUT1 or IOUT2 to AGND.
Output Current Settling Time
R
2R S2
R
2R S3
This is the amount of time it takes for the output to settle to a specified level for a full scale input change. For these devices, it is specifed with a 100 resistor to ground.
Digital to Analog Glitch lmpulse
2R S1
2R S8
2R
R
RFB A IOUTA IOUT B
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal.
Digital Feedthrough
DAC DATA LATCHES AND DRIVERS
Figure 4. Simplified Ladder
When the device is not selected, high frequency logic activity on the device digital inputs is capacitivelly coupled through the device to show up as noise on the IOUT pins and subsequently into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
Access is provided to the VREF, RFB, IOUT1 and IOUT2 terminals of the DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output, bipolar output or in single supply modes of operation. in unipolar mode or four quadrant multiplication in bipolar mode.
Unipolar Mode
This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal, when all 0s are loaded to the DAC.
Harmonic Distortion
Using a single op amp, these devices can easily be configured to provide 2 quadrant multiplying operation or a unipolar output voltage swing as shown in Figure 5. When an output amplifier is connected in unipolar mode, the output voltage is given by: VOUT = -D x VREF Where D is the fractional representation of the digital word loaded to the DAC.
The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonices are included, such as second to fifth. THD = 20log (V22 + V32 + V42 + V52)
V1
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
D = 0 to 256 (8-Bit AD5426) = 0 to 1024 (10-Bit AD5432) = 0 to 4096 (12-Bit AD5443)
VDD R2
When VIN is an ac signal, the circuit performs fourquadrant multiplication. Table II. shows the relationship between digital code and the expected output voltage for bipolar operation (AD5426, 8-Bit device).
C1
Table II. Bipolar Code Table
VDD VREF R1 VREF AD5426/32/43
RFB IOUT1 IOUT2 VOUT = -D VREF
Digital Input
A1
Analog Output (V) +V REF (127/128) 0 -VREF (127/128) -VREF (128/128)
SYNC SCLK SDIN
GND
uController
AGND
1111 1000 0000 0000
1111 0000 0001 0000
NOTES: 1R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
SERIAL INTERFACE
Figure 5. Unipolar Operation
With a fixed 10 V reference, the circuit shown above will give an unipolar 0V to -10V output voltage swing. When VIN is an ac signal, the circuit performs two-quadrant multiplication. The following table shows the relationship between digital code and expected output voltage for unipolar operation. (AD5426, 8-Bit device).
Table I. Unipolar Code Table
The AD5426/AD5432/AD5443 have an easy to use 3-wire interface which is compatible with SPI/QSPI/MicroWire and DSP interface standards. Data is written to the device in 16 bit words. This 16-bit word consists of 4 control bits and either 8, 10 or 12 data bits as shown in Figure 6.The AD5443 uses all 12 bits of DAC data. The AD5432 uses ten bits and ignores the two LSBs, while the AD5443 uses eight bits and ignores the last four bits. As good programming practice, these ignored LSB's should be set to `0'.
Low Power Serial Interface
Digital Input 1111 1000 0000 0000 1111 0000 0001 0000
Analog Output (V) -V REF (255/256) -VREF (128/256) = -VREF/2 -VREF (1/256) -VREF (0/256) = 0
To minimize the power consumption of the device, the interface only powers up fully when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
DAC Control Bits C3 - C0
Bipolar Operation
In some applications, it may be necessary to generate full 4-Quadrant multplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors as shown in Figure 6.
R3 10k VDD VDD VREF AD5426/32/43 SYNC SCLK SDIN RFB IOUT1 IOUT2 R2 C1
Control bits C3 to C0 allow control of various functions of the DAC as can be seen in Table 3. Default settings of the DAC on power on are as follows : Data clocked into shift register on falling clock edges; Daisy chain mode is enabled. Device powers on with zeroscale load to the DAC register and IOUT lines. The DAC control bits allow the user to adjust certain features on power on, for example, Daisy chaining may be disabled if not in use, active clock edge may be changed to rising edge and DAC output may be cleared to either zero
R5 20k R4 10k A2 VOUT = -VREF to +VREF
R1 VREF 10V
A1
GND
uController
AGND NOTES: 1R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3C1 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
Figure 6. Bipolar Operation (4 Quadrant Multiplication)
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
or midscale. The user may also initiate a readback of the DAC register contents for verification purposes.
TABLE 3. DAC CONTROL BITS
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
C2 C1 C0 Funtion Implemented 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 No Operation (Power On Default) Load and Update Initiate Readback Reserved Reserved Reserved Reserved Reserved Reserved Daisy Chain Disable Clock Data to shift register On Rising Edge Clear DAC output to Zero Clear DAC output to Midscale Reserved Reserved Reserved
shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK (this is the default, use the control word to change the active edge) and is valid for the next device on the falling edge (default). By connecting this line to the DIN input on the next device in the chain, a multidevice interface is constructed. 16 clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16N where N is the total number of devices in the chain. See the timing diagram in Figure 3. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data being clocked into the input shift register. A burst clock containing the exact number of clock cycles may be used and SYNC taken high some time later. After the rising edge of SYNC, data is automatically transferred from each device's input shift register to the addressed DAC. When control bits = "0000", the device is in No Operation mode. This may be useful in daisy-chain applications where the user does not wish to change the settings of a particular DAC in the chain. Simply write "0000" to the Control bits for that DAC and the following data bits will be ignored.
Stand alone Mode
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low observing the minimum SYNC falling to SCLK falling edge setup time, t4.
Daisy Chain Mode
Daisy Chain is the default power on mode. To disable the daisy chain function, write "1001" to control word. In Daisy-Chain Mode the internal gating on SCLK is disabled. The SCLK is continuously applied to the input
After power on, write "1001" to control word to disable Daisy Chain Mode. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shited in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. After the falling edge of the 16th SCLK pulse, data will automatically be transferred from the input shift register to the DAC. In order for another serial transfer to take place the counter must be reset by the falling edge of SYNC.
DB0 (LSB)
DB15 (MSB) C3 C2 C1 C0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DATA BITS 0 0
0
0
CONTROL BITS
Figure 6a. AD5426 8 bit Input Shift Register Contents
DB15 (MSB) C3 C2 C1 C0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB0 (LSB) 0 0
CONTROL BITS
DATA BITS
Figure 6b. AD5432 10 bit Input Shift Register Contents
DB15 (MSB) C3 C2 C1 C0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DATA BITS
DB0 (LSB) DB3 DB2 DB1 DB0
CONTROL BITS
Figure 6c. AD5443 12 bit Input Shift Register Contents
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PRELIMINARY TECHNICAL DATA AD5426/AD5432/AD5443
Overview of AD54xx devices Part No Resolution #DACs INL AD5424 AD5425 AD5426 AD5432 AD5433 AD5443 AD5445 8 8 8 10 10 12 12 1 1 1 1 1 1 1 0.5 0.5 0.5 1 1 2 2 Settling Time Interface Package 20ns 20ns 20ns 25ns 25ns 30ns 30ns Parallel Serial Serial Serial Parallel Serial Parallel Features
RU-16, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 Byte Load,10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width RM-10 10 MHz BW, 50 MHz Serial RU-20, CP-20 10 MHz, 10 ns CS Pulse Width
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
10 Lead SOIC (RM-10)
0.122 (3.10) 0.114 (2.90)
10
6
0.122 (3.10) 0.114 (2.90)
1 5
0.199 (5.05) 0.187 (4.75)
PIN 1 0.0197 (0.50) BSC 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) MAX 0.028 (0.70) 0.016 (0.40) 0.120 (3.05) 0.112 (2.85)
0.037 (0.94) 0.031 (0.78)
6 0.006 (0.15) 0.012 (0.30) SEATING 0 PLANE 0.009 (0.23) 0.002 (0.05) 0.006 (0.15) 0.005 (0.13)
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